The usual route for enterprises faced with the need to meet a rising volume of customer and partner interactions on the web has been to employ horizontal scaling by adding more servers at the edge and middle tiers of the typical three-tier architecture. The problem with this approach is at least four-fold: it costs more in power consumption; it costs more in cabling and software patching operations; it costs more in management overhead. Even worse is the fact that today's ultra-fast processors spend much of their time idle, waiting for memory to provide information. The UltraSPARCR T1 processor has been designed to overcome this limitation, as a recent Sun feature article entitled, \'Throughput Computing for Web Services\' explains.

The Sun UltraSPARC T1 processor is the first processor that has been designed for transaction throughput. Instead of focusing on faster processor speeds, which allow for only minimal gains in throughput, the UltraSPARC T1 processor has an architecture that maximizes the throughput of commercial workloads. Its eight cores, each with four distinct processing threads, make the processor a 32-way chip, able to coordinate 32 concurrent processing threads, whether from a combination of processes or from 32 different processes.

"The UltraSPARC T1 chip is built in such a way that the performance can be exploited by any application that has a throughput performance goal," explains Sreeram Duvur, engineering lead for the web services grid initiative at Sun. "The sweet spot is for applications that have a modest to large number of threads or simply rely on multiple processes for scaling." This includes all the popular web and application servers and databases. "...designers were able to put eight cores on a chip and yet run it cool enough that a lot of these servers can be put very close together." The result is a reduction in power and real estate costs with a simultaneous increase in transaction throughput (at a lower cost).

The UltraSPARC T1 processor achieves this gain in throughput by using a fast crossbar switch between cores and a shared L2 cache to speed up thread synchronization and locks by a large factor. The SolarisTM 10 Operating System (Solaris OS) scheduler manages the threads as each of the eight cores pushes four threads through the pipeline in a round-robin fashion. If one thread stalls as a consequence of memory latency, the other threads can use that slot or a new one can be scheduled by the OS, so the processing pipeline remains active. This enables the UltraSPARC T1 processor to mitigate memory latency and allow for near-constant throughput.

A further advantage of the UltraSPARC T1 processor is that it enables web and application tier consolidation, permitting the merging of multiple small web servers and even different tiers in the same server. Ultimately, the UltraSPARC T1 processor offers the ability to reduce the power required by numerous smaller servers with fewer, more efficient and easier to manage servers.

Instead of employing third-party SSL acceleration hardware to deal with encryption and decryption, the UltraSPARC T1 processor contains an integrated Modulo Arithmetic Unit (MAU) in each of its eight cores that works in conjunction with the Solaris Encryption Framework (SEF) to provide dedicated SSL acceleration on the chip itself.

Internal testing at Sun demonstrated that the UltraSPARC T1 processor delivered more RSA operations per second than current generation x86 chips in a competitive dual-processor RISC system. SSL overhead was reduced from 50 percent to six percent over current generation SPARCR processors. The UltraSPARC T1 processor also enables the combination of SSL acceleration with load balancing functions.

The UltraSPARC T1 processor promises to help enterprises consolidate web services architectures, lower data center real estate requirements, decrease energy costs and simplify server management — while witnessing a whole new level of throughput and performance. [...read more...]

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