Apache Design Solutions, provider of physical design integrity solutions for system-on-chip (SoC) designs, has released NSPICE, a new analog circuit simulator targeted for system integrators and designers of chips, boards, connectors and backplanes for the high-speed, multi-gigabit communications, networking and graphics markets. NSPICE is also the simulation backplane for Tomahawk, the company's recently announced flagship product for SoC power network analysis and power integrity.

NSPICE provides several capabilities that have never before been offered in a fully HSPICE compatible simulator. These capabilities include:

• Mixed-domain simulation using direct S-parameters, without translation or use of sub-circuits

• Accurate transient analysis of on-chip PLLs and high-speed drivers combined with off-chip packages and boards

• Signal integrity and nanometer checks for transistor stress, leakage and IR drop

• Higher performance and capacity for simulation of complex nanometer circuits

"NSPICE bridges the gap between chips and systems," said Andrew Yang, founder and CEO of Apache. "Until now, there has been no way to simulate critical high-speed interfaces -- from the chips, to package, to board, to backplane and back again. Now with NSPICE, they can simulate combined on-chip and system effects for a thorough, accurate analysis of very complex environments."

At high frequencies, S-parameter data is the most accurate form of broadband frequency-domain representation. Existing time-domain SPICE methods cannot take in S-parameters directly; the models must be manually fitted or translated into a lumped RLC approximation. NSPICE enables fast and accurate mixed-domain simulation of multi-gigabit serial I/Os by taking in S-parameters directly from the board and simulating them with large on-chip circuits such as high-speed drivers and receivers. By using NSPICE, designers can directly simulate circuits containing hundreds of thousands of transistors and parasitics combining on-chip and off-chip configurations (such as a transmitter + package S-parameters + backplane S-parameters + receiver) that are commonly used in multi-gigabit transceivers, Serdes drivers and gigabit Ethernet applications. NSPICE provides the most accurate simulation of S-parameter data with results confirmed by silicon measurement down to picosecond accuracy across a broad frequency range.

NSPICE considers signal integrity issues during simulation, such as transmission loss, cross-coupling, timing jitter and skew, and IR drop, thereby eliminating the dependency on multiple tools and enabling faster convergence. Emerging nanometer effects such as leakage current, device stress, and headroom are also accounted for.

NSPICE is written in C++ from scratch and employs hierarchical algorithms offering improved performance, memory efficiency and better convergence using advanced matrix solver technology. The product is fully compatible with HSPICE, and SPICE models and netlists. In addition, it supports fast and automatic "eye" diagram generation and viewing.

NSPICE is licensed on the following platforms: SolarisTM Operating Environment (Solaris OE), HP-UX, Linux and Windows 2000. Pricing varies with configuration and platform and starts at $6,000 on a node-locked Windows platform for a one-year, time-based license.

For an evaluation license of NSPICE, register online at:

http://www.apache-da.com/Products/nspice/download.html

sales@apache-da.com

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