Sun's Niagara 3, a one billion-transistor, 16-core processor, and the IBM POWER7 are the subject of Jon Stokes's Ars Technica piece that introduces readers to the floorplan of both chips.

Of the Niagara 3, Stokes writes that it is " ... a great example of modern multiprocessor-turned-SoC (system on a chip), ... focused on pushing large numbers of parallel instruction streams and data streams through the processor socket at once. The shared cache is small, the shared pipes are wide, and the end result is a chip that's all about maintaining a high rate of flow, and not one that's aimed at collecting a large pile of data and chipping away at it with heavy equipment."

The Niagara 3 achieves its notable throughput rate by having each of the 16 individual SPARC cores that make up Niagara 3 support up to eight simultaneous threads of execution, for a total of 128 threads per chip, according to Stokes. The logic of the chip's layout has all of the cores communicate with a unified 6MB L2 cache via a crossbar switch that's placed in the middle of the chip, he writes, for a combination of cores and L2 connected via a switch that forms the basic compute architecture of the SoC.

There are connections from the chip's L2 caches to a variety of I/O interfaces: memory, PCIe, 1G/10G Ethernet, and coherency links. All told, those links can push a total of 2.4Tb/s worth of data through a single Niagara 3 socket, he notes.

Stokes describes the Niagara 3's coherence links as being the equivalent of the QuickPath Interconnect (QPI) on Intel's Nehalem parts, or of HyperTransport for AMD. These links can be used to connect up to four of the chips together without any additional routing chips. He explains that this is what's meant by saying Niagara 3 can be used in a four-socket glueless configuration. Each Niagara 3 chip has two 1.6GHz coherence controllers, which are connected to six coherence links, and each individual link consists of 14 unidirectional lanes that give the link a total bandwidth of 9.6Gb/s, Stokes points out.

The Niagara 3 has two DDR3 memory controllers that are attached to the L2 cache, and each hosts two memory channels, resulting in a total of four channels of DDR3. An additional feature of the Niagara 3 is its PCle controller, which supports two 5Gb/s PCle ports and an Ethernet controller that supports two 1G/10G Ethernet ports.

Stokes's concluding comment observes that both the Niagara 3 and POWER7 will be good for different applications. Sun's Niagara is aimed at networked server operations where lots of simultaneous, lightweight requests have to be serviced—databases, Web servers, and the like. In contrast, POWER7 has the horsepower to grind through a smaller number of more compute-intensive tasks at a high rate of speed. Both parts have their place in the server ecosystem of 2010.

More Information

Sun's Niagara 3 to Feature 16 Cores and 16 Threads per Core [...read more...]

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