Sun architects are making groundbreaking progress towards sophisticated synchronization support for multicore systems, find Dave Dice, Yossi Lev, Mark Moir, Dan Nussbaum, and Marek Olszewski. In their research for a Sun Labs technical report on commercial hardware transactional memory (HTM), the men report on a number of promising results using HTM to improve performance in a variety of contexts, in addition to lessons learned on more effectively using the feature.

Transactional Memory (TM) allows programmers to specify that a block of code should execute without interference from concurrent threads. It alleviates the difficulty of writing multithreaded code, which the researchers acknowledge can be hard to write, understand, and maintain, and may be subjected to difficult tradeoffs. The essence of TM, according to these five, is the ability to ensure that multiple memory accesses can be performed "atomically," so that the programmer does not have to think about these accesses being interleaved with those of another thread.

In the 60-page report, readers are informed about the HTM feature of two revisions of a prototype multicore processor based on Sun's Rock chip. Rock is a multicore SPARC processor that uses aggressive speculation to provide high single-thread performance in addition to high system throughput.

The researchers describe testing used to determine whether transactions succeed and fail in expected cases, and also what feedback Rock gives when a transaction fails. Further, the paper presents results from experiments using HTM in a number of contexts:

• To implement simple operations such as incrementing a counter and a double compare-and-swap (DCAS).

• The use of the DCAS to reimplement some components of the Java concurrency libraries.

• Transactional hash tables and red-black trees using a compiler and library supporting Hybrid TM (HyTM) and Phased TM (PhTM). The researchers note that HyTM and PhTM use HTM to boost performance, but transparently revert to software if unsuccessful. They found significant improvement in success rates for hardware transactions by inserting speculation barriers into the code.

• Development of a novel source-to-source compiler to support inserting speculation barriers in various contexts.

• Transactional lock elision (TLE), which uses HTM to execute lock-based critical sections in parallel if they do not conflict. Experimentation of this technique includes working with simple wrappers in C and C++ programs, as well as with standard lock-based Java code using a modified Java Virtual Machine (JVM).

• Successful use of Rock’s HTM feature to accelerate a parallel Minimum Spanning Forest algorithm.

The technical report contains detailed information about the feedback Rock provides in response to aborted hardware transactions, along with how to improve transaction success rates.

More Information

Early Experience with a Commercial Hardware Transactional Memory Implementation - Sun Labs Technical Report [...read more...]

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