System News
Niagara 2 -- Key Features, Architecture and Diagrams
64-bit, 64-thread SPARC "System on a Chip" based on CMT Architecture
February 19, 2007,
Volume 108, Issue 3

The presentation covers key features of the processor and its architecture, physical implementation (key statistics, on-chip L2 caches, crossbar, clocking scheme, SerDes interfaces, and cryptography support), power and power management and DFT features an
 

Dwayne Lee posted a presentation on his blog on Niagara 2. The presentation is by Umesh Gajanan Nawathe, Mahmudul Hassan, Lynn Warriner, King Yen, Bharat Upputuri, David Greenhill, Ashok Kumar, Heechoul Park of Sun.

Umesh Nawathe is currently a Senior Manager on the Niagara 2 project responsible for global/analog circuits and technology. Umesh has an MS(EE) from University of Michigan, Ann Arbor. He joined SUN about 3 years ago. Prior to that, Umesh held senior technical and management positions working for MIPS/Silicon Graphics designing MIPS processors and Intel before that.

The presentation covers key features of the processor and its architecture, physical implementation (key statistics, on-chip L2 caches, crossbar, clocking scheme, SerDes interfaces, and cryptography support), power and power management and DFT features and test results.

Niagara 2 is the first 64-bit 64-thread SPARC "System on a chip" from Sun based on the power-efficient CMT architecture optimized for Space, Power and Performance (SWaP). It is the successor to Niagara 1, which is known in the market as UltraSPARCR T1. It doubles Niagara 1's throughput performance, significantly improves Floating point throughput performance, has advanced cryptography support and two 10G ethernet ports on chip.

-Niagara 2 Key Features -

  • Second generation chip multi-threading processor optimized for Space, Power and Performance (SWaP)
  • 8 Sparc Cores, 4MB shared L2 cache; Supports concurrent execution of 64 threads
  • Twice UltraSparc T1's throughput performance and performance/Watt
  • Ten times improvement in Floating Point throughput performance
  • Integrates important SOC components on chip: Two 10G Ethernet (XAUI) ports on chip and Advanced Cryptographic support at wire speed
  • On-chip PCI-Express, Ethernet, and FBDIMM memory interfaces are SerDes based

The presentation is 25 pages, and it includes a Niagara 2 block diagram, SPARC Core (SPC) block diagram, a Niagara 2 die micrograph, and more.

See the presentation online. "

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